In many applications, including digital communications, clock and data recovery (CDR) must be performed before data can be decoded. Generally, in a digital clock recovery system, a reference clock signal of a given frequency is generated together with a number of different clock signals having the same frequency but with different phases (also known as a multi-phase clock). In one typical implementation, the different clock signals are generated by applying the reference clock signal to a delay network. Thereafter, one or more of the clock signals are compared to the phase and frequency of an incoming data stream and one or more of the clock signals are selected for data recovery.
A number of existing digital CDR circuits use voltage controlled delay loops (VCDL) to generate a number of clocks having the same frequency and different phase for data sampling (i.e., oversampling). For example, published International Patent Application No. WO 97/14214, discloses a compensated delay locked loop timing vernier. The disclosed timing vernier produces a set of timing signals of similar frequency and evenly distributed phase. An input reference clock signal is passed through a succession of delay stages. A separate timing signal is produced at the output of each delay stage. The reference clock signal and the timing signal output of the last delay stage are compared by an analog phase lock controller. The analog phase lock controller controls the delay of all stages so that the timing signal output of the last stage is phase locked to the reference clock. Based on the results of the oversampled data, the internal clock is delayed so that it provides data sampling adjusted to the center of the “eye.” The phase of the VCDL is adjusted to keep up with phase deviations of the incoming data.
While such voltage controlled delay loops effectively generate the sampling clocks and control the delay stages to maintain alignment of the reference clock signal and the last timing signal, they suffer from a number of limitations, which if overcome, could further improve the utility of such voltage controlled delay loops. For example, when the voltage controlled delay loops are implemented using integrated circuit technology, an inherent mismatch exists between the various delay stages, causing uneven phase distribution of the multi-phase clock in the generated phases of the clock sources. It has been found that even a small processing mismatch can cause a large percentage mismatch in design output variability.
U.S. patent application Ser. No. 11/020,022, entitled, “Trimming Method and Apparatus for Voltage Controlled Delay Loop with Central Interpolator,” discloses methods and apparatus for trimming a desired delay element in a voltage controlled delay loop. While the disclosed trimming process ensures that the delay provided by each delay element in the VCDL loop are the same, each delay element has an associated latch buffer that may not be the same.
A need therefore exists for a trimming method for a voltage controlled delay loop that compensates for such mismatched latch buffers.